Publications

 

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Conference Papers

Journal Papers

Thesis Reports

 

Conference Papers

• H. Mahmoodi, “Reliability Enhancement of Power Gating Transistor under Time Dependent Dielectric Breakdown,” accepted for IEEE/IFIP International Conference on Very Large Scale Integration, Oct. 2012
• A. Guar and H. Mahmoodi, “Impact of Technology Scaling on Performance of Domino Logic in Nano-Scale CMOS,” accepted for IEEE/IFIP International Conference on Very Large Scale Integration, Oct. 2012
• H. Mahmoodi, A. Montoya, J. Franco, C. Rodriguez, J. Carrillo, A. Goel, C. Chen, A. G. Enriquez, H. Jiang, W. Pong, H. Shanasser, “Hands-on Teaching of Embedded Systems Design Using FPGA-Based tPad Development Kit,” Interdisciplinary Engineering Design Education Conference, pp. 1-6, Mar. 2012
• R. Manchaca and H. Mahmoodi, “Impact of Transistor Aging Effects on Sense Amplifier Reliability in Nano-Scale CMOS,” IEEE International Symposium on Quality Electronic Design, pp. 342-346, Mar. 2012
• V. Ganti and H. Mahmoodi, “Comparative Analysis of Copper and CNT Interconnects for H-Tree Clock Distribution,” IEEE International Conference on Computer Design, pp. 447-448, Oct. 2011
• V. G. Rao and H. Mahmoodi, “Analysis of Reliability of Flip-Flops under Transistor Aging Effects in Nano-scale CMOS Technology,” IEEE International Conference on Computer Design, pp. 439-440, Oct. 2011
• F. Moradi, G. Panagopoulos, G. Karakonstantis, D. Wisland, H. Mahmoodi, J.K. Madsen, and K. Roy “Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology,” IEEE International Conference on Computer Design, pp. 439-440, pp. 326-331, Oct. 2011
• F. Moradi, T. V. Cao, D. T. Wisland, S. Aunet, and H. Mahmoodi, “Optimal Body Biasing for Maximizing Circuit Performance in 65nm CMOS Technology,” IEEE International Midwest Symposium on Circuits and Systems, pp. 1-4, Aug. 2011
• W. Pong, A. G. Enriquez, H. Shahnasser, C. C. Cheng, N. M. Ozer, A. S. Cheng, H. Jiang, and H. Mahmoodi, “Enhancing the Interest, Participation, and Retention of Underrepresented Students in Engineering through a Summer Engineering Institute,” American Society for Engineering Education Annual Conference, June 2011
• S. K. Krishnappa and H. Mahmoodi, “Comparative BTI Reliability Analysis of SRAM Cell Designs in Nano-Scale CMOS Technology,” IEEE International Symposium on Quality Electronic Design, pp. 1-6, Mar. 2011
• F. Moradi, C. Augustine, A. Goel, G. Karakonstantis, T. V. Cao, D. Wisland, H. Mahmoodi, and K. Roy, “Data- Dependant Sense-Amplifier Flip-Flop for Low Power Applications,” IEEE Custom Integrated Circuits Conference, pp. 1-4, Sep. 2010
• A. Pushkarna, S. Raghavan, and H. Mahmoodi, “Comparison of Performance Parameters of SRAM Designs in 16nm CMOS and CNTFET Technologies,” IEEE International System-on-Chip Conference, pp. 339-342, Sep. 2010
• A. Shah and H. Mahmoodi, “Thermal Estimation for Accurate Estimation of Impact of BTI Aging Effects on Nano-Scale SRAM Circuits,” IEEE International System-on-Chip Conference, pp. 230-235, Sep. 2010
• L. Liu and H. Mahmoodi, "Evaluation of Power Gating under Transistor Aging Effect Issues in 22nm CMOS Technology," International Conference on Mixed Design of Integrated Circuits and Systems, pp. 477-481, June 2010
• H. Singh and H. Mahmoodi, "Analysis of SRAM Reliability under Combined Effect of NBTI, Process and Temperature Variations in Nano-Scale CMOS," International Conference on Future Information Technology (FutureTech), pp. 1-4, May 2010
• A. Pushkarna and H. Mahmoodi, "Reliability Analysis of Power Gated SRAM under Combined Effects of NBTI and PBTI in Nano-Scale CMOS,"; Great Lake Symposium on VLSI, May 2010
• S. K. Krishnappa, H. Singh, and H. Mahmoodi, "Incorporating Effects of Process, Voltage, and Temperature Variation in BTI Model for Circuit Design," IEEE Latin American Symposium on Circuits and Systems, pp. 236-239, Feb. 2010
• F. Moradi, D. Wisland, H. Mahmoodi, Y. Berg, and T. V. Cao "New SRAM Design Using Body Bias Technique for Ultra Low Power Applications," IEEE International Symposium on Quality Electronic Design, pp. 468-471, Mar. 2010
• F. Moradi, D. T. Wisland, H. Mahmoodi, and T. V. Cao, "Improved Write Margin 6T-SRAM for Low Supply Voltage Applications," IEEE International System-On-Chip Conference, pp. 223-226, Sep. 2009
• E. Lyons, V. Ganti, R. Goldman, V. Melikyan, and H. Mahmoodi, "Full-Custom Design Project for Digital VLSI and IC Design Courses using Synopsys Generic 90nm CMOS Library," International Conference on Microelectronic Systems Education, pp. 45-48, July 2009
• F. Moradi, D. Wisland, H. Mahmoodi, T. V. Cao, and M. Zarre Dooghabadi, "Adaptive Supply Voltage Circuit using Body Biasing Technique," International Conference on Mixed Design of Integrated Circuits and Systems, pp. 215-219, June 2009
• F. Moradi, D. T. Wisland, H. Mahmoodi, S. Aunet, T. V. Cao, and A. Peiravi "Ultra Low Power Full Adder Topologies,"; IEEE International Symposium on Circuits and Systems, pp. 3158-3161, May 2009
• H. Mahmoodi and A. Jalali, "Virtual Age: Enabling Technologies and Trends," International Conference on Information Technology: New Generations, pp. 999-1004, April 2009
• F. Moradi, D. T. Wisland, H. Mahmoodi, A. Peiravi, S. Aunet, and T. V. Cao, "New Subthreshold Design Concepts in 65nm CMOS Technology," IEEE International Symposium on Quality Electronic Design, pp. 162-166, Mar. 2009
• F. Moradi, D. T. Wisland, T. V. Cao, A. Peiravi, and H. Mahmoodi “1-Bit Sub Threshold Full Adders in 65nm CMOS Technology,” International Conference on Microelectronics, pp. 268-271, Dec. 2008
• A. Jalali and H. Mahmoodi, “Virtual Age: Next Wave of Change in Society,” International Conference on e-Commerce, e-Administration, e-Society, and e-Education, pp. 1593-1605, Jan. 2009
• F. Moradi, D. T. Wisland, S. Aunet, H. Mahmoodi, T. V. Cao, “65nm Sub-Threshold 11T-SRAM for Ultra Low Voltage Applications,” IEEE International Systems-On-Chip Conference, pp. 113-118, Sep. 2008
• F. Moradi, D. T. Wisland, H. Mahmoodi, T. V. Cao, “High Speed and Leakage-Tolerant Domino Circuits for High Fan-in Applications in 70nm CMOS Technology,” International Caribbean Conference on Device, Circuits, and Systems, pp.1-5, April 2008
• F. Moradi, H. Mahmoodi, and H. Alimohammadi, “A Leakage-tolerant CMOS Comparator in Ultra Deep Submicron CMOS Technology,” XXII Conference on Design of Circuits and Integrated Systems, pp. 415-418, Nov. 2007
• S. Paul, S. Bhunia, and H. Mahmoodi, “Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points,” IEEE International Conference on Computer Aided Design, pp. 401-404, Nov. 2007
• K. Kim, H. Mahmoodi, and K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling Technique,” International Symposium on Low Power Electronic Design, pp. 177 – 182, Aug. 2007
• V. Tirumalashetty and H. Mahmoodi, “Clock Gating and Negative Edge Triggering for Energy Recovery Clock,” IEEE International Symposium on Circuits and Systems, pp. 1141-1144, May 2007
• Rajani Kuchipudi and Hamid Mahmoodi, “Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS,” IEEE International Symposium on Quality Electronic Design, pp. 27-32, Mar. 2007
• J. Yeung and H. Mahmoodi, “Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies,” IEEE International Systems-On-Chip Conference, pp. 261-264, Sep. 2006
• F. Moradi, A. Peiravi, and H. Mahmoodi “A Novel Leakage-Tolerant Domino Logic Circuit with Feedback from Footer Transistor in Ultra Deep Submicron CMOS,” IEEE International Conference on Mixed Design of Integrated Circuits and Systems, pp. 210-213, June 2006
• S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, “Self-Repairing SRAM for Reducing parametric Failures in Nanoscaled Memory,” Symposium on VLSI Circuits, pp. 132-133, June. 2006
• N. Banerjee, S. Bhunia, H. Mahmoodi, and K. Roy, “Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating” Design, Automation, and Test in Europe, vol. 1, pp. 1 – 6, Mar. 2006
• K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI Devices for Low-Power and High-Performance Applications,” International Conference on VLSI Design, pp. 8, Jan. 2006
• A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, “Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability,” Asia and South Pacific Design Automation Conference, pp. 6, Jan. 2006
• K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI Devices for Low-Power and High-Performance Applications,” IEEE/ACM International Conference on Computer Aided Design, pp. 217-224, Nov. 2005
• S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM,” IEEE Asian Test Symposium, pp. 176-181, Dec. 2005
• T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Independent Gate Skewed Logic in Double-Gate SOI Technology,” IEEE International SOI Conference, pp. 83-84, Oct. 2005
• N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, "Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis," IEEE International Conference on Computer Design, pp. 206-211, Oct. 2005
• S. Mukhopadhayay, K. Kang, H. Mahmoodi, and K. Roy, “Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring,” International Test Conference, pp. 10, Nov. 2005
• M. Meterelliyoz, H. Mahmoodi, and K. Roy, “A Leakage Control System for Thermal Stability During Burn-In Test,” International Test Conference, pp. 10, Nov. 2005

 

 

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Journal Papers

• B. Afzal, B. Ebrahimi, A. Afzali-Kusha, and H. Mahmoodi, “Modeling Read SNM Considering Both Soft Oxide Breakdown and Negative Bias Temperature Instability,” Microelectronics Reliability,” accepted for Elsevier Microelectronics Reliability Journal
• M. Houshmand Kaffashian, R. Lotfi, K. Mafinezhadand, and H. Mahmoodi, “Impacts of NBTI/PBTI on Performance of Domino Logic Circuits with High-k Metal-Gate Devices in Nanoscale CMOS,” Elsevier Microelectronics Reliability Journal, DOI: 10.1016/j.microrel.2012.03.012, Apr. 2012.
• M. Houshmand Kaffashian, R. Lotfi, K. Mafinezhadand, and H. Mahmoodi, “Impact of NBTI on Performance of Domino Logic Circuits in Nano-Scale CMOS,” Elsevier Microelectronics Journal, vo.l 42, no. 12, pp. 1327-1334, Dec. 2011.
• F. Morado, S. K. Gupta, G. Panagopoulos, D. T. Wisland, H. Mahmoodi, and K. Roy “Asymmetrically-Doped FinFETs for Low-Power Robust SRAMs,” IEEE Transactions on Electron Devices, vol. 58, no. 12, Dec. 2011.
• M. Houshmand Kaffashian, R. Lotfi, K. Mafinezhadand, and H. Mahmoodi, “An Optimization Method for NBTI-Aware Design of Domino Logic Circuits in Nano-Scale CMOS,” IEICE Electronics Express, vol. 8, no. 17, pp. 1406-1411, Aug. 2011
• M. Cho, J. Schlessman, H. Mahmoodi, M. Wolf, and S. Mukhopadhyay, “Post-Silicon Adaptation for Low-Power SRM under Process Variation,” IEEE Design and Test of Computers, vol. 27, no. 6, pp. 26-35, Nov. 2010
• S. Paul, H. Mahmoodi, and S. Bhunia, “Low-Overhead Fmax Calibration at Multiple Operating Points Using Delay Sensitive Based Path Selection,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 2, pp. , Feb. 2010
• H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra Low Power Clocking Scheme Using Energy Recovery and Clock Gating," IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 1, pp. 33-44, Jan 2009
• Y. Wang, H. Mahmoodi, L-Y. Chiou, H. Choo, J. Park, W. Jeong, and K. Roy, “Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering,” Journal of Signal Processing Systems, Dec. 2008
• S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, "Arbitrary Two-Pattern Delay Testing Using A Low-Overhead Supply Gating," Journal of Electronic Testing Theory and Applications, June 2008
• K. Kim, H. Mahmoodi, and K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 446-458, Feb. 2008
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Reduction of Parametric Failures in Sub-100nm SRAM Array using Body Bias," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 174-183, Jan. 2008
• A. Datta, A. Goel, T. Cakici, H. Mahmoodi, D. Lekshmanan, and K. Roy, “Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 1957-1966, Nov. 2007
• S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, “Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1370-1382, June 2007
• N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, "A Novel Low-Overhead Operand Isolation Technique for Low-Power Datapath Synthesis," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 9, pp. 1034-1039, Sep. 2006
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "A Novel High Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 2, pp. 183-192, Feb. 2006
• Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, “Efficient Testing of SRAM with Optimized March Sequences and a Novel DFT Technique for Emerging Failures due to Process Variations,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 11, pp. 1286-1295, Nov. 2005
• H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1787-1796, Sep. 2005
• S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled CMOS," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, pp. 1859-1880, Dec. 2005

 

 

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Thesis Reports

• B. Wu “ Time Dependent Breakdown of Gate Oxide and Prediction of Oxide Gate Lifetime ,” March 2012
• H. Vakhariya “ Datapath Architecture for Reliable Computing In Nano-Scale Technology ,” Jan. 2012
• E. Lyons “ Low Power Scanner for High-Density Electrode Array Neural Recording ,” Sept. 2011
• M. Randhawa “ Analysis of Impact of Transistor Aging Effects on Clock Skew in Nano-Scale Cmos ,” 2011
• P. Vadali “Electronic Realization of Human Brain’s Neo-Cortex Column Using Fpga,”Dec. 2010
• M. Ram “Reliability Analysis of Dynamic Logic Circuits under Transistor Aging Effects in Nanotechnology,” Dec 2010
• S. Krishnappa “Comparative Analysis of Sram Cell Designs in Nano-Scale Technology,” Aug. 2010
• E. Pataky “Design of an Application-Specific Instruction Processor for the GFM Scuba Diving Algorithm,” Dec. 2009
• H. Singh “Analysis of SRAM Reliability under Combined Effect of Transistor Aging, Process and Temperature Variations in Nano-Scale CMOS,” Dec. 2009
• V. Tirumalashetty “Low Power Design Of Digital Systems Using Energy Recovery Clocking and Clock Gating,” Oct. 2007

 

 

 

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